High-performance ECC decoder
US9136871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2014 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Feb 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/617
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.