Systems and methods to mitigate phase noise
US9137065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices are described for mitigating phase noise. An output of a decoder is utilized to generate an estimation of a plurality of transmitted symbols. One or more phase errors of a plurality of received symbols are generated. The one or more phase errors are based at least in part on the estimation of the plurality of transmitted symbols. The one or more phase errors are generated by comparing angles between the plurality of received symbols and the estimation of the plurality of transmitted symbols. The output of the decoder used to generate the estimation is a plurality of a posteriori log-likelihood ratios (LLRs) of a plurality of transmitted bits. The estimation is generated by performing hard decision decoding on the output of the decoder and remodulating the hard decision decoding according to the modulation used by a transmitter on the plurality of transmitted bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.