Memory-mapped buffers for network interface controllers
US9137179B2 · kind B2 · utility
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13References
20Claims
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Key dates
| Filing date | Jul 26, 2006 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jul 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing network interface controllers (NICs) with memory-mapped buffers are described. A processing system includes a plurality of processing cells, each including at least one processor and at least one system memory. A NIC is associated with each of the processing cells for transmitting and receiving data between the processing cells. Each of the cells further includes a memory interconnect to which the NIC is directly connected and the NIC includes at least one memory-mapped buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.