All optical processing circuit for conflict resolution and switch configuration in a 2×2 optical node
US9137591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2007 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Mar 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2011/0058
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An optical processing circuit, such as a combinatorial network, comprises an arrangement of optical logic gates suitable for use in combination with a switched optical node of the kind having at least first and second input ports and two output ports, the node being configurable into either a cross or a bar configuration, and in which the optical processing circuit is arranged so as to receive at least three optical input signals which respectively comprise a packet identifier signal PIH which identifies whether or not a first input signal is present at the first input port of the switched optical node, the first input port being assigned a higher priority than the second input port, a first destination address AH indicating the output port of the switched optical node to which a first information carrying signal, received at the first input port, is intended to be passed, and a second destination address AL indicating the output port of the switched optical node to which a second information carrying signal, received at the second input port, is intended to be passed, and in which the processing circuit is configured to generate from these three optical input signals the following…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.