Sense amplifier offset voltage reduction
US9140747B2 · kind B2 · utility
53Cited by
14References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jul 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.