Methods for light coupling into power semiconductors
US9140864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Oct 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4214
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a method of coupling light into a power semiconductor device having a semiconductor structure with two or more layers. The power semiconductor device has multiple cells of functionally identical units linked by multiple interconnects. In each device unit, a patterned electrode layer is disposed on the surface of the semiconductor structure. The method includes illuminating the power semiconductor device by directing a light from a light source through the patterned electrode layer to form an enhanced light coupling with the semiconductor structure. The patterned electrode layer is configured to have a micron scaled grid pattern having multiple metal grids and aperture openings that is based on a distributed resistance model having two characteristic current decay lengths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.