Method and apparatus to schedule store instructions across atomic regions in binary translation
US9141362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jan 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.