Master circuits having dynamic priority leads coupled with memory controller
US9141561B2 · kind B2 · utility
4Cited by
5References
4Claims
0Family size
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Key dates
| Filing date | Nov 8, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes multiple master devices and at least one memory refresh scheduler. When a master device needs higher priority for memory access, the master device sends a dynamic priority signal to the memory refresh scheduler and in response, the memory refresh scheduler changes its policy for issuing refresh commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.