Proportional memory operation throttling
US9141568B2 · kind B2 · utility
4Cited by
22References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2011 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.