Direct memory access controller
US9141572B2 · kind B2 · utility
4Cited by
24References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Nov 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.