Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags
US9141586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprises a floating point unit (FPU) to generate a plurality of status flags for a rounded value of a finite nonzero number. The plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number. The plurality of status flags comprises an overflow flag and an underflow flag. The FPU determines whether a rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, the FPU calculates the rounded value of the finite nonzero number based on an overflow rounding. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.