Efficient placement of texture barrier instructions
US9142005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | May 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for placing texture barrier instructions within a thread program to advantageously enable efficient and correct operation of the thread program. A thread program compiler statically determines a pending request count needed to progress beyond a particular texture barrier instruction, which blocks execution of subsequent instructions that depend on previously requested data. Each instance of the thread program blocks execution at the barrier instruction until a pending request count condition is satisfied. This technique may advantageously reduce power consumption in a graphics processing unit by eliminating power consumption associated with conventional, generalized scoreboard resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.