Pipelining in a memory
US9142270B2 · kind B2 · utility
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2References
18Claims
0Family size
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Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Sep 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.