Non-volatile semiconductor memory device
US9142307B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Mar 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and a bit line coupling circuit coupled between the bit line and the sense amplifier circuit. The bit line coupling circuit includes a first bit line coupling transistor in an outer layout area of the bit line coupling circuit and a second bit line coupling transistor in an inner layout area of the bit line coupling circuit. The first bit line coupling transistor has a longer distance in a channel length direction or in a channel width direction between an impurity diffused layer coupled to the bit line and an element isolation area than the second bit line coupling transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.