Semiconductor nano layer structure and manufacturing method thereof
US9142410B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jul 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/221
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for manufacturing a semiconductor nano layer structure includes: two substrates are provided; a plurality of semiconductor nanowires are formed on one of the substrates; an absorption surface is formed on the other substrate; one of the substrates is fixed on a cylindrical roller, the cylindrical roller is brought into contact with a surface of the substrate which is stationary and is not fixed on the cylindrical roller, and rolled with a constant velocity and pressure so that the semiconductor nanowires are break, detached, transferred and absorbed, and a semiconductor nano layer structure is formed on the stationary substrate; a de-laminating process is performed to separate the semiconductor nano layer structure from the second substrate; an electric Joule heat welding process is locally performed to bond each of the semiconductor nanowires of the semiconductor nano layer structure or each semiconductor nano layer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.