Calibration of inter-slice gain and offset errors in time-interleaved analog-to- digital converter
US9143147B1 · kind B1 · utility
17Cited by
4References
24Claims
0Family size
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Key dates
| Filing date | Jul 3, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.