Rate matching and scrambling techniques for control signaling
US9143167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.