Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges
US9143346B1 · kind B1 · utility
1Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Oct 31, 2010 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Oct 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6418
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.