Apparatus, systems, and methods for providing configurable computational imaging pipeline
US9146747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Mar 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.