Patent · US Active

Synchronous semiconductor memory device having dual delay locked loop circuit and method of managing dual delay locked loop circuit

US9147452B2 · kind B2 · utility

1Cited by

8References

20Claims

0Family size

Assignee

SAMSUNG ELECTRONICS CO., LTD. · KR

Inventor

Taesik Na · Seoul, KR

Key dates

Filing date	Mar 13, 2014
Grant date	Sep 29, 2015
Priority date	—
Expiry date	Mar 27, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2272
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A synchronous semiconductor memory device includes a first delay locked loop circuit and a second delay locked loop circuit. The first delay locked loop circuit has a first delay line and generates a first clock hat is delay-synchronized with a clock applied as a signal for a data output timing control. The second delay locked loop circuit has a second delay line and generates a second clock that is delay-synchronized with the clock. The first delay locked loop circuit consumes less power than the second delay locked loop circuit, and the second delay locked loop circuit has less jitter than the first delay locked loop circuit. The first and second delay locked loop circuits operate at different logic levels for a delay synchronization operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.