Transistor device and fabrication method
US9147614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k dielectric layer. A functional layer can be formed on the fluorinated high-k dielectric layer and a metal layer can be formed on the functional layer to fill the trench with the metal layer. Due to fluorination of the high-k dielectric layer, negative bias temperature instability of the formed transistor can be reduced and oxygen vacancies can be passivated to reduce positive bias temperature instability of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.