Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
US9147652B2 · kind B2 · utility
4Cited by
2References
8Claims
0Family size
Assignee
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Key dates
| Filing date | May 19, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | May 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.