Device with FD-SOI cell and insulated semiconductor contact region and related methods
US9147695B2 · kind B2 · utility
3Cited by
5References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Dec 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.