Symmetric is linear equalization circuit with increased gain
US9148087B1 · kind B1 · utility
89Cited by
51References
19Claims
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Inventor
Key dates
| Filing date | May 16, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.