Dual comparator-based error correction scheme for analog-to-digital converters
US9148159B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.