Pipelined ADC having error correction
US9148161B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A stage of a pipelined analog-to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. A mapping circuit can exchange inputs between selected ones of the first and second pluralities of DACs, and a calibration circuit can provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlate to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.