Information processor and control network system
US9148297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Aug 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/437
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.