Digital I/Q imbalance compensation in a quadrature receiver
US9148328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2011 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Mar 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2694
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method reduce distortion in a processed signal. The apparatus includes a first receive path, a second receive path, a summation unit, and a compensation unit. The first receive path is configured to process a received analog signal into a first digital signal. The second receive path is configured to process the received analog signal with a phase shift into a second digital signal. The summation unit is configured to sum the first and second digital signals to form a processed digital signal. The compensation unit is configured to identify a conjugate of the processed digital signal, apply a weighting factor to the conjugate of the processed digital signal to form a weighted signal, and subtract the weighted signal from the processed digital signal to reduce the distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.