Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values
US9152382B2 · kind B2 · utility
2Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Sep 29, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.