Multi-core processor system
US9152482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2014 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Apr 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/548
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a multi-core processor system, including: multiple central processor units and multiple groups of level-one hardware message queues. Each central processor unit is separately connected to a group of level-one hardware message queues and is configured to process messages in the level-one hardware message queues. Each group of level-one hardware message queues includes multiple level-one hardware message queues. Moreover, in each group of level-one hardware message queues, a level-one hardware message queue having a higher priority is scheduled preferentially, and level-one hardware message queues having the same priority are scheduled in a round-robin manner according to round robin scheduling weights. Through the multi-core processor system provided in the present invention, the efficiency and performance of the multi-core processor system are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.