Hidden surface removal in graphics processing systems
US9153070B2 · kind B2 · utility
6Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The early depth test stages 4, 13 of a graphics processing pipeline 1 are configured to broadcast information 9, 10, 11, 14 about fragments, etc., that pass those early depth tests to other stages 3, 4, 6, 12 in the pipeline. The other stages in the pipeline then use the early depth test pass information to determine if the processing of any fragments that they are currently processing can be stopped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.