Memory and method of operating the same
US9153302B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Mar 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.