Fatigue management system and method for hybrid nonvolatile solid state memory system
US9153337B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2009 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Feb 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.