Body bias circuits and methods
US9154123B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2014 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Aug 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.