Dynamic offset injection for CMOS ADC front-end linearization
US9154146B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2014 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems employing a digital background calibration technique for linearizing the front-end circuits of IF-sampling ADCs. The disclosed systems and methods employ a power series model to eliminate the static non-linearity with split-ADC architecture and LMS algorithm for background learning. The present disclosure utilizes a technique for applying two different offset signals to the input of two conversion paths in the split-ADC architecture. When the system nonlinearity is successfully calibrated, the output difference between the two conversion paths results in a fixed offset that is identical to the offset injected at the input. The disclosed digital background calibration technique can linearize the front-end circuits of high-speed ADCs and significantly reduce power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.