Apparatus and method to compensate for data skew for multiple memory devices and adjust delay for individual data lines based on an optimized critical window
US9158330B1 · kind B1 · utility
3Cited by
1References
18Claims
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Key dates
| Filing date | Nov 15, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Dec 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for processing systems capable of compensating for data skew are disclosed. An example apparatus can include delay circuitry that includes a plurality of delay devices each being individually adjustable to produce an individual delay for each data line with each data line including branches of different lengths leading to different memory devices, and memory control circuitry coupled to the delay circuitry and configured to determine, for each data line, an individual delay based on an optimized critical window, the optimized critical window being based on multiple chip select signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.