Link clock change during veritcal blanking
US9158350B2 · kind B2 · utility
1Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.