Multi-input memory command prioritization
US9158715B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Sep 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are memory apparatuses, and methods of operating the same, that have a memory array module configured, in a given clock cycle, to either receive a first command to write to a first memory location having a first address, or receive a second command to read from a second memory location having a second address. A comparison circuit of the memory apparatus is configured to compare the first address to the second address. The memory apparatus also includes an output circuit configured to output data stored in the memory array module at the second memory location based at least on the first address and second address being different. The output circuit is also configured to output data received from a write data input, bypassing the memory array module, when the first address and the second address are the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.