Optimizing lithography masks for VLSI chip design
US9158876B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a computer-implemented method includes accessing mask input data. The mask input data includes a mathematical representation of a mask in a mask representation space, where the mask is configured to create an integrated circuit microprocessor. A set of values is obtained based on a derivative of the mask input data. The set of values is optimized, by a computer processor, in a derivative domain to obtain optimized mask data. The optimized mask data is transformed into the mask representation space to obtain printable mask output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.