Method and apparatus for content addressable memory parallel lookup
US9159420B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Aug 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for a content addressable memory. A system includes a common memory module configured to store a plurality of entries, ones of the entries being defined by a string of bits. A first parallel compare logic unit is configured to compare a first lookup key against a plurality of entries stored in the memory module in a first memory operation cycle and to output a match indication indicating a match between the first lookup key and the string of bits of an entry from among the plurality of entries. A second parallel compare logic unit is configured to compare, in the first memory operation cycle, a second lookup key against the plurality of entries stored in the memory module and to output a match indication indicating a match between the second lookup key and the string of bits of an entry from among the plurality of entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.