Testing system and testing method thereof
US9159451B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Nov 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.