Semiconductor device and method of manufacturing semiconductor device
US9159607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Sep 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3656
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.