Thin film transistor array panel and manufacturing method thereof
US9159839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.