Patent · US Active

Adaptive interface for coupling FPGA modules

US9160338B2 · kind B2 · utility

0Cited by

2References

15Claims

0Family size

Assignee

dSPACE digital signal processing and control engineering GmbH · DE

Inventors

Dirk Hasse · Paderborn, DE
Robert Polnau · Paderborn, DE

Key dates

Filing date	May 12, 2014
Grant date	Oct 13, 2015
Priority date	—
Expiry date	May 12, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17744
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.