System and method for phase recovery with selective mitigation of timing corruption due to digital receiver equalization
US9160582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03146
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.