Techniques for tiling arrays of pixel elements

US9163995B2 · kind B2 · utility

Assignees

• Santa Barbara Infrared, Inc · US
• Research Triangle Institute · US
• Indiana Integrated Circuits, LLC · US

Inventors

• Joseph D LaVeigne · Buellton, US
• John Lañnon · Raleigh, US
• Scott Goodwin · Chapel Hill, US
• Jason M. Kulick · South Bend, US

Key dates

• Filing date: Oct 21, 2012
• Grant date: Oct 20, 2015
• Expiry date: Nov 12, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/49117
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Sub-arrays such as tiles or chips having pixel elements arranged on a routing layer or carrier to form a larger array. Through-chip vias or the like to the backside of the chip are used for connecting with the pixel elements. Edge features of the tiles may provide for physical alignment, mechanical attachment and chip-to-chip communication. Edge damage tolerance with minimal loss of function may be achieved by moving unit cell circuitry and the electrically active portions of a pixel element away from the tile edge(s) while leaving the optically active portion closer to the edge(s) if minor damage will not cause a complete failure of the pixel. The pixel elements may be thermal emitter elements for IR image projectors, thermal detector elements for microbolometers, LED-based emitters, or quantum photon detectors such as those found in visible, infrared and ultraviolet FPAs (focal plane arrays), and the like. Various architectures are disclosed.