Single-sided distributed cache system
US9164702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Feb 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/463
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed cache system including a data storage portion, a data control portion, and a cache logic portion in communication with the data storage and data control portions. The data storage portion includes memory hosts, each having non-transitory memory and a network interface controller in communication with the memory for servicing remote direct memory access requests. The data control portion includes a curator in communication with the memory hosts. The curator manages striping of data across the memory hosts. The cache logic portion executes at least one memory access request to implement a cache operation. In response to each memory access request, the curator provides the cache logic portion a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts through the corresponding network interface controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.