Self-timed logic bit stream generator with command to run for a number of state transitions
US9164730B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Apr 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/584
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.