Managing out-of-order memory command execution from multiple queues while maintaining data coherency
US9164908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2015 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.