Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit
US9165679B2 · kind B2 · utility
8Cited by
20References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Oct 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.